1. Technical Field of the Invention
The technology presented herein is related to: a solid-state image capturing element, which is constituted of a semiconductor element for performing a photoelectric conversion on and capturing an image of image light from a subject, a method for driving the solid-state image capturing element, and a method for manufacturing the solid-state image capturing element, and more particularly, to a solid-state image capturing element such as a MOS type image sensor capable of being driven with low electric power consumption, a method for driving the solid-state image capturing element, and a method for manufacturing the solid-state image capturing element; and an electronic information device, such as a digital camera (e.g., a digital video camera or a digital still camera), an image input camera (e.g., a monitoring camera), a scanner, a facsimile machine, a television telephone device and a camera-equipped cell phone device, including the solid-state image capturing element as an image input device used in an image capturing section thereof
2. Description of the Related Art
For example, CCD type solid-state image capturing elements, MOS type solid-state image capturing elements and other semiconductor image sensors are excellent for mass production, and therefore, have been conventionally used as image input devices in digital cameras, such as digital video cameras and digital still cameras, camera-equipped cell phone devices and other portable electronic information devices.
Such conventional portable electronic information devices are driven by batteries, and therefore, it is important to achieve the lowering of the voltage of the driving electricity and the lowering of the electric power consumption. Further, it is also important to achieve the lowering of the cost and the reduction of the module size.
For this reason, in the field of solid-state image capturing elements used in portable electronic information devices, the MOS type solid-state image capturing elements consume less electric power than the CCD type solid-state image capturing elements. In addition, by using conventional CMOS processing technologies, the cost reduction becomes possible. By forming sensor elements and their peripheral circuit elements on the same chip, the reduction of the module size becomes possible. With such and other advantages, the MOS type solid-state image capturing elements are being more focused on.
In addition, the conventional MOS type solid-state image capturing elements with a buried photodiode as a light signal detecting section are remarkably advantageous in terms of achieving noise reduction, and can obtain high quality images.
FIG. 9(a) is a longitudinal cross sectional view of a conventional MOS type solid-state image capturing element disclosed as a conventional example in Reference 1, illustrating the solid-state image capturing element for one pixel. FIGS. 9(b) and 9(c) are each a potential distribution diagram illustrating a transferring path for signal charges, which consists of a photoelectric conversion and accumulation section, a channel region below a gate electrode, and an electric charge detecting section and is taken along a dotted line a-a′ in FIG. 9(a). FIG. 9(b) is a potential distribution diagram in a case where a transfer pulse φTX applied to a transfer gate electrode is at a low level. FIG. 9(c) is a potential distribution diagram in a case where the transfer pulse φTX applied to a transfer gate electrode is at a high level.
FIGS. 9(a) and 9(b) illustrate a conventional type MOS type image sensor 100 with a buried photodiode and a case where a transfer pulse φTX applied to a transfer gate electrode 106 is at a low level. Herein, a photoelectric conversion and accumulation section 103 formed in a p-type well region 102 is separated from a surface of a semiconductor substrate by a p-type pinning layer 104 in the surface of the semiconductor substrate. This prevents noise electric charges, which are generated at an interface between the p-type well region 102 and an insulation film 105 formed in a semiconductor substrate 101, from flowing into the photoelectric conversion and accumulation section 103 to be a dark voltage component.
However, in a case where the transfer pulse φTX applied to a transfer gate electrode 106 is at a high level as illustrated in FIG. 9(c), the p-type pinning layer 104 in the surface of the semiconductor substrate has an influence on the electric charge transferring path a-a′, and a potential barrier is formed, which is an obstructing barrier for the transferring of light signal charges from the photoelectric conversion and accumulation section 103 to an electric charge detecting section 107.
Owing to the potential barrier, signal charges remain in the photoelectric conversion and accumulation section 103 and the signal charges from the photodiode cannot be transferred completely when the signal charges are read out. This condition causes problems such as the production of noise, difficulty in the noise reduction, and the creation of after images.
In order to prevent such after images from being created, Reference 1 discloses a method for changing a positional relationship between the photoelectric conversion and accumulation section 103 and the high concentration, p-type pinning layer 104 thereabove with relation to the transfer gate electrode 106, as in FIGS. 10(a) to 10(c).
FIG. 10(a) is a longitudinal cross sectional view of another conventional MOS type solid-state image capturing element disclosed as a conventional example in Reference 1, illustrating the solid-state image capturing element for one pixel. FIGS. 10(b) and 10(c) are each a potential distribution diagram illustrating a transferring path for signal charges, which consists of a photoelectric conversion and accumulation section, a channel region below a transfer gate electrode, and an electric charge detecting section and is taken along the dotted line a-a′ in FIG. 10(a). FIG. 10(b) is a potential distribution diagram in a case where a transfer pulse φTX applied to a transfer gate electrode is at a low level. FIG. 10(c) is a potential distribution diagram in a case where the transfer pulse φTX applied to a transfer gate electrode is at a high level.
A MOS type image sensor 100A illustrated in FIG. 10(a) includes an overlapping structure, where a transfer gate electrode 106 overlaps a photoelectric conversion and accumulation section 103A. Therefore, as illustrated in FIG. 10(c), the potential barrier illustrated in FIG. 9(c) is cleared away and the after images can be suppressed.
Since the photoelectric conversion and accumulation section 103A has the overlapping structure with respect to the transfer gate electrode 106, the above-described electric barrier is cleared away by a tip portion of the photoelectric conversion and accumulation section 103A being extended below the transfer gate electrode 106. On the other hand, the extending width of the tip portion of the photoelectric conversion and accumulation section 103A becomes wider below the transfer gate electrode 106 as illustrated in FIG. 10(a) when the concentration of the photoelectric conversion and accumulation section 103A is increased in order to sufficiently secure an accumulatable capacity of the electric charges. As a result, a charge reservoir as circled by a dotted line in FIG. 10(c) is formed below the transfer gate electrode 106, which causes a problem of creating an after image.
In order to solve the problem, Reference 1 proposes a MOS type solid-state image with a cross sectional structure as illustrated in FIG. 11(a).
FIG. 11(a) is a cross sectional view of a transferring path for signal charges from a photodiode section to an electric charge detecting section via a transferring transistor in a conventional MOS type solid-state image capturing element disclosed in Reference 1 (in the case of 0≦b≦c). FIGS. 11(b) and 11(c) are each a potential distribution diagram illustrating a transferring path for signal charges, which consists of a photoelectric conversion and accumulation section, a channel region below a transfer gate electrode, and an electric charge detecting section and is taken along a dotted line a-a′ in FIG. 11(a). FIG. 11(b) is a potential distribution diagram in a case where a transfer pulse φTX applied to a transfer gate electrode is at a low level. FIG. 11(c) is a potential distribution diagram in a case where the transfer pulse φTX applied to a transfer gate electrode is at a high level. In FIG. 11, note that the members having the same function and effect as the corresponding ones in FIGS. 9 and 10 are added with the same reference numerals for explanation.
In a unit pixel section in a MOS type image sensor 100B as illustrated in FIGS. 11(a) to 11(c), a p-type pinning layer 104 is formed offset such that a tip portion thereof is shifted with respect to a photoelectric conversion and accumulation section 103B. Herein, the photoelectric conversion and accumulation section 103B is formed extending up to below a transfer gate electrode 106, overlapping the transfer gate electrode 106 (in a plan view). Owing to this, in the electric charge transferring path from the photoelectric conversion and accumulation section 103B to an electric charge detecting section 107 (FD), the formation of a potential barrier is suppressed, which can be seen in the conventional MOS type image sensor 100 illustrated in FIG. 9(c).
As illustrated in FIG. 10(c), the charge reservoir is formed in the conventional MOS type image sensor 100A. However, in the case where the photoelectric conversion and accumulation section 103B overlaps the transfer gate electrode 106, a p-type well region 102C is formed closer to the electric charge detecting section 107 (FD) with respect to the photoelectric conversion and accumulation section 103B in the MOS type solid-state image capturing element 100B. As a result, an n-type low concentration semiconductor region 101B of an n-type semiconductor substrate 101 remains existing between the photoelectric conversion and accumulation section 103B and the p-type well region 102C. Thus, compared to the cross sectional structure in FIG. 10(a), the overlapping width of the photoelectric conversion and accumulation section 103B over the transfer gate electrode 106 the distance illustrated by the arrow b in FIG. 11(a)) can be narrower, thereby avoiding the conventional formation of the charge reservoir that causes after images.
As described above, the MOS type solid-state image capturing element 100B in FIG. 11 and disclosed in Reference 1 can transfer electric charges completely from the photodiode section to the electric charge detecting section 107 to obtain high quality images, in which noise and after images are further suppressed.
FIG. 12 is a longitudinal cross sectional view of a conventional. MOS type solid-state image capturing element disclosed in Reference 2, illustrating the MOS type solid-state image capturing element for one pixel.
In FIG. 12, a conventional MOS type solid-state image capturing element 200 includes: an N type photodiode region 203 formed in a P type well 202 above a silicon substrate 201; a gate electrode 204, one end of which is adjacent to the photodiode region 203; an N type drain region 205, which is adjacent to the other end of the gate electrode 204; and an element separating region 206, which has an STI structure surrounding the photodiode region 203, gate electrode 204 and drain region 205 in a plan view. The thickness of a gate oxide film 207, which is located directly below the gate electrode 204, is 10 nm or less. A portion on one end of the gate electrode 204 overlaps the photodiode region 203.
In addition, a first region 211, a second region 212, and a third region 213 are formed in this order on the surface side of the substrate from the photodiode region 203 to the drain region 205 via the channel region below the gate electrode 204. The first region 211 is disposed with a predetermined distance from one end of the gate electrode 204 and has a P type first concentration C1. The second region 212 has a P type second concentration C2 and one end thereof is adjacent to the first region 211 and the other end overlaps the gate electrode 204. The third region 213 has a P type third concentration C3 and one end thereof is adjacent to the second region 212 and the other end is adjacent to the drain region 205. The relationship among the concentrations C1 to C3 herein is as follows: first concentration C1>second concentration C2>third concentration C3; or first concentration C1=second concentration C2>third concentration C3. As such, it becomes possible to obtain the MOS type solid-state image capturing element 200 in which the reading characteristics becomes favorable at a low voltage, and white spots, dark current and other image defects are suppressed sufficiently.
In a solid-state image capturing element and a method for driving the solid-state image capturing element disclosed in Reference 3, it is proposed that a negative voltage of −0.5 V or less (e.g., −1 V) is applied to a transfer gate electrode during the accumulation of electric charges, so that a hole channel is formed in an interface of an oxide film directly below the transfer gate electrode to reduce dark noise (dark voltage and white detects).
Reference 1: Japanese Laid-Open Publication No. 2008-66480
Reference 2: Japanese Laid-Open Publication No. 2005-123395
Reference 3: Japanese Patent No. 3724374